1. Field of the Invention
This invention relates to integrated circuits, and more particularly relates to dynamically allocating circuit exercise among used and unused circuit islands on integrated circuit wafers so as to keep localized physical parameters, such as island-to-island thermal gradients, within nominal value ranges across the wafers.
2. Description of the Prior Art
The integrated circuit industry deploys a number of techniques for keeping integrated circuits comfortably protected from physical failure mechanisms, chief of which is heat. There are a number of mechanisms for keeping integrated circuit modules within operating temperatures appropriate for trouble-free operation. These include such techniques as requiring warm-up periods, providing air or liquid cooling of modules, and requiring air conditioned environments. These techniques tend to be permanent global solutions for great groups of circuit modules mounted together in gates. Attention is paid also to the heat dissipation characteristics of wafers in individual integrated circuit modules, but aside from heat sinks there is relatively little deployment of physical parameter control mechanisms below the module level, even through there may be hundreds or even thousands of circuit devices on the wafer. Current practice is to dice a round semiconductor wafer into a number of rectangular chips for mounting in modules, but the trend is toward larger, even full-wafer, chips. For purposes of this patent specification, the term "wafer" describes the block of semiconductor material upon which circuit devices are arrayed, regardless of size or shape.
The integrated circuit industry is constantly attempting to resolve the problem of yield detractors. Yield detractors in the semiconductor industry are failure mechanisms which render a wafer unsuitable for deployment in a product because one or more included circuits are inoperative or subject to malfunction. The yield of unsable wafers completed as a function of wafers started through the process is a very important parameter in measuring success in semiconductor manufacture. Typical yield detractors are: pipes in the semiconductor; defects in the insulator; defects in the photolithographic process. As the level of integration increases, through making individual circuits smaller and through making the wafer larger, the probability of a defect occurring rises. The yield diminishes. Process quality improvement may not be able to provide acceptable yields of perfect integrated circuit wafers. Fault bypass techniques may be required, so that circuit wafers may be used even though having one or more faults. Fault bypass techniques reassign operational duty from a bad circuit island to a normally redundant equivalent good circuit island.
As is known in the art of integrated circuits, the wafer may be relatively large, up to full slice of a semiconductor boule, now ranging from 50 to 100 millimeters in diameter or greater. The wafer may include a great number of circuit islands, which islands may be considered merely as groups physically located together in a locality of the wafer. The island may, for example, be a quadrant, or may be a quadrant of a quadrant, or other defined locality in a grid of localities.
The integrated circuit industry has reported a number of fault bypass techniques, in which a redundant circuit island is activated to take the operational duty from a circuit island in which a fault occurs. The circuit islands for fault bypass equivalency may be called "islands." A favored fault bypass technique is opposed complementary island replacement, in which islands of mirror symmetric circuits on facing primary and secondary wafers may take over the operational duty of their related mirror twins in case of fault. There is no physical replacement similar to a light bulb replacement; the duty is reassigned analogous to switching on a light bulb in an equivalent nearby fixture.
Wafer geography, and the fact that wafer interconnections are relatively giant as contrasted to logic circuitry, limit the number of interconnections available for wafer to wafer connection. Linear shear stresses resulting from differential thermal expansion of opposed complementary wafers may also limit wafer to wafer connections to a relatively small area of the wafer. Placing controlled collapse wafer connections at widely separated locations over the face of the wafer is subject to the problem of differential thermal expansion of the opposed complementary wafers, with resulting connection failures due to fatigue failure of one or more controlled collapse wafer connections. Also, non-planarity of the mating surfaces may result in failure of controlled collapse solder balls to bridge the resulting gap during the reflow process.
Physical stress is a known problem, and is known to be primarily due to heat buildup as a function of circuit exercise. Temperature gradients, between islands of the same wafer, are known; normal heat dissipation techniques do not fully prevent exercise-related hot or cool circuit islands within a wafer. Much effort has been directed to cooling, including prevention by cooling of hot spots on a wafer, but very little beyond warmup has beend one to create island-to-island temperature balance and balance of other physical parameters. Physical parameters of redundant circuit islands have generally been ignored.
The following items are representative of the prior art: U.S. Pat. No. 3,879,839, Logue, Method of Manufacturing Multi-Function LSI Wafers, Apr. 29, 1975, shows an opposed complementary wafer mirror symmetric island fault replacement technique.
U.S. Pat. No. 3,984,860, Logue, Multi-Function LSI Wafers, Oct. 5, 1976, a division of U.S. Pat. No. 3,879,839, similarly shows an opposed complementary wafer mirror symmetric island fault replacement technique. Logue et al. "Techniques for Improving Engineering Productivity of VLSI Designs," IBM Journal of Research and Development, Volume 25, Nos. 2-3, May 1981, pages 107-115, shows a very large scale integration design approach based on the use of programmed logic array macros and a laser beam for rapid personalization and repairing of design errors.
These prior developments by the inventor and associates, while important, do not teach nor suggest the present invention, which electronically provides physical condition balancing between primary and secondary islands across wafers, regardless of whether the islands are good operational, good redundant or bad.
In the opposed complementary wafer island technique of fault bypass, the defective islands are relieved of duty for operational circuit exercise, not by means of a mechanical or chemical process, but by being disconnected by logic and power gates. Since the wafers are mirror symmetric, the controlled collapse wafer connections associated with each island and its mirror twin island of logic match up. Logic gates and power gates previously designed into both the primary wafer and the mirror symmetric secondary wafer are then used to reroute signals through global wiring that is mirror duplicated on each wafer to allocate logical circuit exercise to operational islands and to bypass good redundant islands as well as to bypass faulty islands.